Publications

Journal Articles (h-index = 28, Google Scholar)

57) F. A. McGuire, Y. -C. Lin, K. Price, G. B. Rayner, S. Khandelwal, S. Salahuddin, and A. D. Franklin, "Sustained sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors," Nano Lett., (in press), 2017.

56) K. M. Price, K. E. Schauble, F. A. McGuire, D. B. Farmer, and A. D. Franklin, "Uniform growth of sub-5-nanometer high-k dielectrics on MoS2 using plasma-enhanced atomic layer deposition," ACS Appl. Mater. Interfaces, vol. 9, pp. 23072-23080, 2017.

55) J. B. Andrews, C. Cao, M. Brooke, and A. D. Franklin, "Noninvasive material thickness detection by aerosol jet printed sensors enhanced through metallic carbon nanotube ink," IEEE Sensors Journal, vol. 17, pp. 4612-4618, 2017.

54) M. J. Catenacci, P. F. Flowers, C. Cao, J. B. Andrews, A. D. Franklin, and B. J. Wiley, "Fully printed memristors from Cu-SiO2 core-shell nanowire composites," J. Electronic Mater., vol. 46, pp. 4596-4603, 2017.

53) C. Cao, J. B. Andrews, and A. D. Franklin, "Completely printed, flexible, stable and hysteresis-free carbon nanotube thin-film transistors via aerosol jet printing," Adv. Electron. Mater., vol. 3, pp. 1700057, 2017.

52) N. D. Cox, C. D. Cress, J. E. Rossi, I. Puchades, A. Merrill, A. D. Franklin, and B. J. Landi, "Modification of silver/single-wall carbon nanotube electrical contact interfaces via ion irradiation," ACS Appl. Mater. Interfaces, vol. 9, pp. 7406-7411, 2017.

51) D. Joh, F. McGuire, R. Abedini-Nassab, J. Andrews, R. Achar, Z. Zimmers, D. Mozhdehi, R. Blair, F. Albarghouthi, W. Oles, J. Richter, C. Fontes, A. Hucknall, B. Yellen, A. D. Franklin, and A. Chilkoti, “Poly(oligo(ethylene glycol) methyl ether methacrylate) brushes on high-k metal oxide dielectric surfaces for bioelectrical environments,” ACS Appl. Mater. Interfaces, vol. 9, pp. 5522-5529, 2017.

50) S. Najmaei, S. Lei, R. Burke, B. M. Nichols, A. George, P. M. Ajayan, A. D. Franklin, J. Lou, and M. Dubey, “Enabling ultra-sensitive photo-detection through control of interface properties in molybdenum disulfide atomic layers,” Sci. Rep., vol. 6, pp. 39465, 2016.

49) F. A. McGuire, Z. Cheng, K. Price, and A. D. Franklin, "Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer," Appl. Phys. Lett., vol. 109, pp. 093101, 2016.

48) Z. Cheng, J. A. Cardenas, F. McGuire, S. Najmaei, and A. D. Franklin, "Modifying the Ni-MoS2 contact interface using a broad-beam ion source," IEEE Electron Device Lett., vol. 37, pp. 1234-1237, 2016.

47) C. Cao, J. B. Andrews, A. Kumar, and A. D. Franklin, "Improving contact interfaces in fully printed carbon nanotube thin-film transistors," ACS Nano, vol. 10, pp. 5221-5229, 2016. *correction to published Rc values is here

46) A. D. Franklin, "Nanomaterials in transistors--From high-performance to thin-film applications," Science, vol. 349, pp. aab2750, 2015.

45) J. Li, A. D. Franklin, and J. Liu, "Gate-free electrical breakdown of metallic pathways in single-walled carbon nanotube crossbar networks," Nano Lett., vol. 15, pp. 6058-6065, 2015.

44) Q. Cao, S. -J. Han, J. Tersoff, A. D. Franklin, Y. Zhu, Z. Zhang, G. S. Tulevski, J. Tang, and W. Haensch, "End-bonded contacts for carbon nanotube transistors with low, size-independent resistance," Science, vol. 350, pp. 68-72, 2015.

43) C. -S. Lee, E. Pop, A. D. Franklin, W. Haensch, and H. -S. P. Wong, "A compact virtual-source model for carbon nanotube field-effect transistors in the sub-10-nm regime--Part II: Extrinsic elements, performance assessment, and design optimization," IEEE Trans. Electron Devices, vol. 62, pp. 3070-3078, 2015.

42) C. -S. Lee, E. Pop, A. D. Franklin, W. Haensch, and H. -S. P. Wong, "A compact virtual-source model for carbon nanotube field-effect transistors in the sub-10-nm regime--Part I: Intrinsic elements," IEEE Trans. Electron Devices, vol. 62, pp. 3061-3069, 2015.

41) G. S. Tulevski, A. D. Franklin, D. Frank, J. M. Lobez, Q. Cao, H. Park, A. Afzali, S. -J. Han, J. B. Hannon, and W. Haensch, "Toward high-performance digital logic technology with carbon nanotubes," ACS Nano, vol. 8, pp. 8730-8745, 2014.

40) A. D. Franklin, D. B. Farmer, and W. Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors,”ACS Nano, vol. 8, pp. 7333-7339, 2014.

39) B. Kim, A. D. Franklin, C. Nuckolls, W. Haensch, and G. S. Tulevski, “Achieving low-voltage thin-film transistors using carbon nanotubes,” Appl. Phys. Lett., vol. 105, pp. 063111, 2014.

38) D. Shahrjerdi, A. D. Franklin, S. Oida, J. A. Ott, G. S. Tulevski, and W. Haensch, “High-performance air-stable n-type carbon nanotube transistors with erbium contacts,” ACS Nano, vol. 7, pp. 8303-8308, 2013. 

37) A. D. Franklin, “The road to carbon nanotube transistors,” Nature, vol. 498, pp. 443-444, 2013.

36) A. D. Franklin, S. O. Koswatta, D. B. Farmer, J. T. Smith, L. Gignac, C. M. Breslin, S. -J. Han, G. S. Tulevski, H. Miyazoe, W. Haensch, and J. Tersoff, “Carbon nanotube complementary wrap-gate transistors,” Nano Lett., vol. 13, pp. 2490-2495, 2013.

35) J. Luo, L. Wei, C. -S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, and H. -S. P. Wong, “A compact model for carbon nanotube field-effect transistors including non-idealities and calibrated with experimental data down to 9 nm gate length,” IEEE Trans. Electron Devices, vol. 60, pp. 1834-1843, 2013. 

34) J. T. Smith, A. D. Franklin, D. B. Farmer, and C. Dimitrakopoulos, “Reducing contact resistance in graphene devices through contact area patterning,” ACS Nano, vol. 7, pp. 3661-3667, 2013. 

33) G. S. Tulevski, A. D. Franklin, and A. Afzali-Ardakani, “High purity isolation and quantification of semiconducting carbon nanotubes via column chromatography,” ACS Nano, vol. 7, pp. 2971-2976, 2013.

32) A. D. Franklin, S. Oida, D. B. Farmer, J. T. Smith, S. -J. Han, C. M. Breslin, and L. Gignac, “Stacking graphene channels in parallel for enhanced performance with the same footprint,” IEEE Electron Device Lett., vol. 34, pp. 556-558, 2013.

31) A. D. Franklin, N. A. Bojarczuk, and M. Copel, “Consistently low subthreshold swing in carbon nanotube transistors using lanthanum oxide,” Appl. Phys. Lett., vol. 102, pp. 013108, 2013.

30) A. D. Franklin, S. Koswatta, D. B. Farmer, G. S. Tulevski, J. T. Smith, H. Miyazoe, and W. Haensch, “Scalable and fully self-aligned n-type carbon nanotube transistors with gate-all-around,” IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 4.5.1-4.5.4, 2012.

29) H. Park, A. Afzali, S. -J. Han, G. S. Tulevski, A. D. Franklin, J. Tersoff, J. B. Hannon, and W. Haensch, “High-density integration of carbon nanotubes via chemical self-assembly,” Nature Nanotechnol., vol. 7, pp. 787-791, 2012. 

28) Q. Cao, S. -J. Han, G. S. Tulevski, A. D. Franklin, and W. Haensch, “Evaluation of Field-Effect Mobility and Contact Resistance of Transistors That Use Solution-Processed Single-Walled Carbon Nanotubes,” ACS Nano, vol. 6, pp. 6471-6477, 2012.

27) S. -J. Han, D. Reddy, G. D. Carpenter, A. D. Franklin, and K. A. Jenkins, “Current Saturation in Submicrometer Graphene Transistors with Thin Gate Dielectric: Experiment, Simulation, and Theory,” ACS Nano, vol. 6, pp. 5220-5226, 2012.

26) A. D. Franklin, G. S. Tulevski, S. -J. Han, D. Shahrjerdi, Q. Cao, H. -Y. Chen, H. -S. P. Wong, and W. Haensch, “Variability in carbon nanotube transistors--Improving device-to-device consistency,” ACS Nano, vol. 6, pp. 1109-1115, 2012.

25) A. D. Franklin, M. Luisier, S. -J. Han, G. Tulevski, C. M. Breslin, L. Gignac, M. S. Lundstrom, and W. Haensch, “Sub-10 nm carbon nanotube transistor,” Nano Lett., vol. 12, pp. 758-762, 2012.

24) A. D. Franklin, S. -J. Han, A. A. Bol, and V. Perebeinos, “Double contacts for improved performance of graphene transistors,” IEEE Electron Device Lett., vol. 33, pp. 17-19, 2012.

23) A. D. Franklin, S. -J. Han, G. S. Tulevski, M. Luisier, C. M. Breslin, L. Gignac, M. S. Lundstrom, and W. Haensch, “Sub-10 nm carbon nanotube transistor,” IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 23.7.1-23.7.3, 2011.

22) S. -J. Han, A. Valdes-Garcia, A. Bol, A. D. Franklin, D. Farmer, K. A. Jenkins, and W. Haensch, “Graphene technology with inverted-T gate and RF passives on 200mm platform,” IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 2.2.1-2.2.4, 2011.

21) D. Shahrjerdi, A. D. Franklin, S. Oida, G. S. Tulevski, S. -J. Han, J. B. Hannon, and W. Haensch, “High device yield carbon nanotube NFETs for high-performance logic applications,” IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 23.3.1-23.3.4, 2011.

20) A. D. Franklin, “Replacing silicon with carbon nanotubes--Why it’s still worth considering,” EE Web Pulse Magazine, issue 13, pp. 8-10, 2011.

19) S. -J. Han, K. A. Jenkins, A. V. Garcia, A. D. Franklin, A. A. Bol, and W. Haensch, “High-frequency graphene amplifier,” Nano Lett., vol. 11, pp. 3690-3693, 2011.

18) A. D. Franklin, S. -J. Han, A. A. Bol, and W. Haensch, “Effects of nanoscale contacts to graphene,” IEEE Electron Device Lett., vol. 32, pp. 1035-1037, 2011.

17) S. -J. Han, J. Chang, A. D. Franklin, A. A. Bol, R. Loesing, D. Guo, G. S. Tulevski, W. Haensch, and Z. Chen, “Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates,” IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 9.1.1-9.1.4, 2010.

16) A. D. Franklin and Z. Chen, “Length scaling of carbon nanotube transistors,” Nature Nanotechnol., vol. 5, pp. 858-862, 2010.

15) A. D. Franklin, A. Lin, H. -S. P. Wong, and Z. Chen, "Current scaling in aligned carbon nanotube array transistors with local bottom gating," IEEE Electron Device Lett., vol. 31, pp. 644-646, 2010.

14) R. A. Sayer, S. Kim, A. D. Franklin, S. Mohammadi, and T. S. Fisher, "Shot noise thermometry for thermal characterization of templated carbon nanotubes," IEEE Trans. Components and Packaging Technol., vol. 33, pp. 178-183, 2010.

13) T. L. Westover, A. D. Franklin, B. A. Cola, T. S. Fisher, and R. G. Reifenberger, "Photo- and thermionic emission from potassium-intercalated carbon nanotube arrays," J. Vac. Sci. Technol. B, vol. 28, pp. 423-434, 2010.

12) A. D. Franklin, G. Tulevski, J. B. Hannon, Z. Chen, “Can carbon nanotube transistors be scaled without performance degradation?IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 23.1.1-23.1.4, 2009.

11) A. D. Franklin, R. A. Sayer, T. D. Sands, D. B. Janes, and T. S. Fisher, "Vertical carbon nanotube devices with nanoscale lengths controlled without lithography," IEEE Trans. Nanotechnol., vol. 8, pp. 469-476, 2009.  (COVER ARTICLE)

10) A. D. Franklin, R. A. Sayer, T. D. Sands, T. S. Fisher, and D. B. Janes, "Toward surround gates on vertical single-walled carbon nanotube devices," J. Vac. Sci. Technol. B, vol. 27, pp. 821-826, 2009.

9) J. C. Claussen, A. D. Franklin, A. Haque, D. M. Porterfield, and T. S. Fisher, "Electrochemical biosensor of nanocube-augmented carbon nanotube networks," ACS Nano, vol. 3, pp. 37-44, 2009.  (COVER ARTICLE)

8) A. D. Franklin, D. B. Janes, J. C. Claussen, T. S. Fisher, and T. D. Sands, "Independently addressable fields of porous anodic alumina embedded in SiO2 on Si," Appl. Phys. Lett., vol. 92, pp. 013122, 2008.

7) R. Voggu, C. S. Rout, A. D. Franklin, T. S. Fisher, C. N. R. Rao, "Extraordinary sensitivity of the electronic structure and properties of single-walled carbon nanotubes to molecular charge-transfer," J. Phys. Chem. C, vol. 112, pp. 13053-13056, 2008.

6) J. T. Smith, Q. Hang, A. D. Franklin, D. B. Janes, and T. D. Sands, "Highly ordered diamond and hybrid triangle-diamond patterns in porous anodic alumina thin films," Appl. Phys. Lett., vol. 93, pp. 043108, 2008.

5) A. D. Franklin, J. T. Smith, T. S. Fisher, T. D. Sands, K.-S. Choi, and D. B. Janes, “Controlled decoration of single-walled carbon nanotubes with Pd nanocubes,” J. Phys. Chem. C, vol. 111, pp. 13756-13762, 2007.

4) A. D. Franklin, M. R. Maschmann, M. DaSilva, D. B. Janes, T. S. Fisher, and T. D. Sands, “In- place fabrication of nanowire electrode arrays for vertical nanoelectronics on Si substrates,” J. Vac. Sci. Technol. B, vol. 25, pp. 343-347, 2007.

3) M. R. Maschmann, A. D. Franklin, T. D. Sands, and T. S. Fisher, “Optimization of porous anodic Al-Fe-Al structures for carbon nanotube synthesis,” Carbon, vol. 45, pp. 2290-2296, 2007.

2) A. D. Franklin, M. R. Maschmann, A. Scott, D. B. Janes, T. D. Sands, and T. S. Fisher, “Lithography-free in situ Pd contacts to templated single-walled carbon nanotubes,” Nano Lett., vol. 6, pp. 2712-2717, 2006.

1)  M. R. Maschmann, A. D. Franklin, P. B. Amama, D. N. Zakharov, E. A. Stach, T. D. Sands, and T. S. Fisher, “Vertical single- and double-walled carbon nanotubes grown from modified porous anodic alumina templates,” Nanotechnology, vol. 17, pp. 3925-3929, 2006.

 

Book Chapters

1) A. D. Franklin, “Carbon nanotube electronics,” Emerging Nanoelectronic Devices, ed. A. Chen, John Wiley & Sons, Ltd, (in press), 2013.

2) A. D. Franklin, M. R. Maschmann, and T. S. Fisher, “Integration of vertical carbon nanotube devices,” Encyclopedia of Semiconductor Nanotechnology, ed. A. Umar, American Scientific Publishers, (in press), 2012.

 

Invited Talks

45) Symposium on VLSI Technology, "Scaling, stacking, and printing: How 1D and 2D nanomaterials still hold promise for a new era of electronics," Kyoto, Japan, June 2017.

44) Illumina, "Scaling, printing, and sensing: A new era for electronics made possible using nanomaterials," San Diego, CA, Jan. 2017.

43) Brigham Young University, “Scaling, printing, and sensing: A new era for electronics made possible using nanomaterials,” Provo, UT, Oct. 2016.

42) IBM T. J. Watson Research Center, “Scaling, printing, and sensing: A new era for electronics made possible using nanomaterials,” Yorktown Heights, NY, July 2016.

41) International Symposium on Devices and Applications of Two-Dimensional Materials, “Stacking, damaging, and etching: Optimizing performance in 2D electronic devices,” Fudan University, Shanghai, China, July 2016.

40) Emerging Technologies CMOS 2016 Conference, “Promises and challenges of nanomaterial in transistors: From high-performance to thin-film applications,” Montreal, Quebec, Canada, May 2016.

39) TechConnect World 2016 – Nanotech, Microtech, Biotech, Cleantech, “Promises, problems, and practicalities of nanomaterials in transistors,” National Harbor, MD, May 2016.

38) Phi Theta Kappa Honors Society General Meeting, “How the world works: Global perspectives,” Mesa Community College, Mesa, AZ, Mar. 2016.

37) BYU Management Society – Phoenix-East Chapter, “The hidden truth behind our explosive technological revolution,” Arizona State University, Tempe, AZ, Mar. 2016.

36) University of Minnesota, “Promises, problems, and practicalities for nanomaterials in transistors,” Minneapolis, MN, Mar. 2016.

35) University of Notre Dame, "Promises, problems, and practicalities for nanomaterial transistors," South Bend, IN, Jan. 2016.

34) MRS-ASM-AVS Joint Symposium, "Nanomaterials in Electronics," NC State, Raleigh, NC, Nov. 2015.

33) 41st Micro and Nano Engineering (MNE) conference, "Promises, problems, and practicalities of nanomaterial electronics," The Hague, Netherlands, Sept. 2015.  - KEYNOTE SPEAKER - 

32) Eindhoven University of Technology, "What role will nanomaterials play in electronics?" Eindhoven, Netherlands, Sept. 2015.

31) Illumina, "The pillars of nanomaterial-enabled devices: Purity, placement, and performance," San Diego, CA, Aug. 2015.

30) North Carolina State University, "What role will nanomaterials play in electronics?" Raleigh, NC, June 2015.

29) Army Research Laboratory (ARL), "Nanomaterials in the next switch?" Adelphi, MD, Apr. 2015.

28) University of North Carolina at Chapel Hill, "What role will nanomaterials play in electronics?" Chapel Hill, NC, Apr. 2015.

27) Government Microcircuit Applications & Critical Technology Conference (GOMAC Tech), "Nanomaterials in the next switch?" St. Louis, MO, Mar. 2015.

26) American Chemical Society (ACS) Meeting, "How will carbon nanotubes impact the next generation of electronics?" Denver, CO, Mar. 2015.

25) Gordon Research Conference—Nanostructure Fabrication, “Prospects for bottom-up 1D and 2D nanoelectronics in high-performance computing,” Biddeford, ME, Jul. 2014.

24) TechConnect World 2014 – Nanotech, Microtech, Biotech, Cleantech, “Prospects and challenges for carbon nanotube transistors in high performance nanoelectronics beyond 2020,” National Harbor, MD, June 2014.

23) Device Research Conference (DRC) - Rump Session, "What are 2D devices and materials good for?" Santa Barbara, CA, Jun. 2014.

22) 1st International Workshop on Data-Abundant System Technology, “Latest advancements toward a carbon nanotube transistor technology,” Stanford University, Palo Alto, CA, Apr. 2014.

21) Columbia University, “Next generation transistors: Where do carbon nanotubes fit in?,” New York, NY, Mar. 2014.

20) Duke University, “Next generation transistors: Where do carbon nanotubes fit in?,” Durham, NC, Feb. 2014

19) International Semiconductor Device Research Symposium, “Latest developments toward a carbon nanotube transistor technology,” Bethesda, MD, Dec. 2013.

18) Lithography Workshop, “Patterning needs and obstacles for a sub-10 nm carbon nanotube transistor technology,” La Quinta, CA, Nov. 2013.

17) International Conference on Solid State Devices and Materials (SSDM), “Wrapping carbon nanotubes in a gate-all-around geometry,” Fukuoka, Japan, Sept. 2013.

16) National Institute of Advanced Industrial Science and Technology (AIST), “The road ahead for transistors: Where do carbon nanotubes fit in?,” Tsukuba, Japan, Sept. 2013.

15) Symposium on Recent Advances in Carbon-Based Nanoelectronics, “Scaling carbon nanotube transistors for a sub-10 nm digital technology,” Peking University, Beijing, China, Jul. 2013.

14) Purdue University, “The road ahead for carbon nanotube transistors,” West Lafayette, IN, Jun. 2013.

13) Arizona State University, “The road ahead for transistors: Where do carbon nanotubes fit in?” Tempe, AZ, Jun. 2013.

12) Material Research Society (MRS) Spring Meeting, “Nanoscale contacts to carbon nanomaterials,” San Francisco, CA, Apr. 2013.

11) Stanford University, “Carbon nanotube transistor technology--Are we there yet?!,” Palo Alto, CA, Apr. 2013.

10) UC Berkeley, “Carbon nanotube transistor technology,” Berkeley, CA, Apr. 2013.

9) CNTs for Digital Electronics Workshop, “Scaling and variability,” NIST, Gaithersburg, MD, Sept. 2012.

8) Gordon Research Conference - Nanostructure Fabrication, “Carbon Nanotubes for a New Generation of Transistors,” University of New England, Biddeford, ME, Jul. 2012.

7) Georgia Institute of Technology - MSE Seminar Series, “Carbon Nanotubes--Why They’re Still Worth Pursuing for Next-Generation Transistors,” Atlanta, GA, Mar. 2012.

6) IBM Materials Research Community, “Promises and Challenges for Achieving a Digital Technology with Carbon Nanotube Transistors,” Yorktown Heights, NY, Mar. 2012.

5) NYS Meeting of the American Physical Society, “Carbon Nanotubes:  Can They Really Replace Silicon?” University of Albany, NY, Apr. 2011.

4) Lester Eastman Conference on High Performance Devices, “Interfacing with Carbon Nanomaterials--Difficulties in Accessing the Intrinsic Properties,” Rensselaer Polytechnic Institute, NY, Aug. 2010.

3) University of Notre Dame, “Carbon Nanotube Transistors: The Future?” Notre Dame, IN, Mar. 2009.

2) Arizona State University, “Toward Manufacturable Vertical Carbon Nanotube Nanoelectronic Devices,” Tempe, AZ, Nov. 2008.

1) IBM T. J. Watson Research Center, “Templated Vertical Carbon Nanotubes for Nanoelectronics,” Yorktown Heights, NY, Sept. 2008.

 

Contributed Conference Presentations

41) K. M. Price, F. A. McGuire, and A. D. Franklin, "Plasma-enhanced atomic layer deposition of sub-5 nm high-k dielectrics on 2D crystals," 17th International Conference on Atomic Layer Deposition (ALD 2017), Denver, CO (2017).

40) F. A. McGuire, Y. -C. Lin, B. Rayner, and A. D. Franklin, "MoS2 negative capacitance FETs using CMOS-compatible hafnium zirconium oxide," Device Research Conference, Univ. Notre Dame, Notre Dame, IN (2017).

39) Z. Cheng, K. M. Price, and A. D. Franklin, "Edge contacts to multilayer MoS2 using in situ Ar ion beam," Device Research Conference, Univ. Notre Dame, Notre Dame, IN (2017).

38) K. M. Price and A. D. Franklin, "Integration of 3.4 nm HfO2 into the gate stack of MoS2 and WSe2 top-gate field-effect transistors," Device Research Conference, Univ. Notre Dame, Notre Dame, IN (2017).

37) Y.-C. Lin, F. McGuire, and A. D. Franklin, "Capping layers and thermal annealing effects of ferroelectric and antiferroelectric Hf0.5Zr0.5O2 for transistor applications," Materials Research Society (MRS) Fall Meeting, Boston, MA (2016).

36) C. Cao, J. Andrews, and A. D. Franklin, "Full printing of all layers in carbon nanotube thin-film transistors using aerosol jet printing," Materials Research Society (MRS) Fall Meeting, Boston, MA (2016).

35) K. Price, F. McGuire, K. Schauble, and A. D. Franklin, "Growth of ultrathin high-k dielectrics on 2D crystals using plasma-enhanced ALD," Materials Research Society (MRS) Fall Meeting, Boston, MA (2016).

34) C. Cao, J. B. Andrews, and A. D. Franklin, "Improving contact interfaces in fully printed carbon nanotube thin-film transistors," ASME International Mechanical Engineering Congress & Exposition (IMECE), Tampa, FL (2016).

33) Z. Cheng, J. A. Cardenas, F. McGuire, and A. D. Franklin, "Using Ar ion beam exposure to improve contact resistance in MoS2 FETs," Device Research Conference, Univ. Delaware, Newark, DE (2016).

32) Z. Cheng, J. A. Cardenas, F. McGuire, and A. D. Franklin, "Improving Contact Resistance in MoS2 Transistors by Interface Modification with a Low-Energy Ion Beam," Materials Research Society (MRS) Fall Meeting, Boston, MA (2015).

31) F. McGuire, Z. Cheng, and A. D. Franklin, "Toward Low-Voltage Operation in 2D Transistors Using Integrated Ferroelectric Polymers with MoS2," Materials Research Society (MRS) Fall Meeting, Boston, MA (2015).

30) A. D. Franklin and W. Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors,” Device Research Conference, UC-Santa Barbara, Santa Barbara, CA (2014).

29) A. D. Franklin, S. Koswatta, D. B. Farmer, G. S. Tulevski, J. T. Smith, H. Miyazoe, and W. Haensch, “Scalable and fully self-aligned n-type carbon nanotube transistors with gate-all-around,” IEEE International Electron Device Meeting (IEDM), Washington, DC (2012).

28) H. Park, A. Afzali, S. -J. Han, G. S. Tulevski, A. D. Franklin, J. Tersoff, J. B. Hannon, and W. Haensch, “Selective placement of individual carbon nanotubes and fabrication of high-density field-effect transistors,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2012).

27) Q. Cao, S. -J. Han, G. S. Tulevski, A. D. Franklin, and W. Haensch, “Evaluation of field-effect mobility and contact resistance of transistors that use solution-processed single-walled carbon nanotubes,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2012).

26) G. S. Tulevski, A. D. Franklin, and B. Kim, “Isolation and quantification of high-purity semiconducting carbon nanotubes via column chromatography,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2012).

25) J. T. Smith, A. D. Franklin, and C. D. Dimitrakopoulos, “Enhancing carrier injection into graphene through contact area patterning,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2012).

24) A. D. Franklin, S. Oida, and D. Farmer, “Stacked graphene channels in a field-effect transistor,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2012).

23) A. D. Franklin, S. -J. Han, G. S. Tulevski, M. Luisier, C. M. Breslin, L. Gignac, M. S. Lundstrom, and W. Haensch, “Sub-10 nm carbon nanotube transistor,” IEEE International Electron Device Meeting (IEDM), Washington, DC (2011).

22) S. -J. Han, A. Valdes-Garcia, A. Bol, A. D. Franklin, D. Farmer, K. A. Jenkins, and W. Haensch, “Graphene technology with reversed-T gate and RF passives on 200mm platform,” IEEE International Electron Device Meeting (IEDM), Washington, DC (2011).

21) D. Shahrjerdi, A. D. Franklin, S. Oida, G. S. Tulevski, S. -J. Han, J. B. Hannon, and W. Haensch, “High device yield carbon nanotube NFETs for high-performance logic applications,” IEEE International Electron Device Meeting (IEDM), Washington, DC (2011).

20) A. D. Franklin, D. Shahrjerdi, G. S. Tulevski, S. -J. Han, and W. Haensch, “Scaling to sub-100 nm contacts in graphene and carbon nanotube transistors,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2011).

19) G. S. Tulevski, B. Chandra, and A. D. Franklin, “Highly-enriched semiconducting carbon nanotubes for the fabrication of electronic devices,” 219th ECS Meeting, Montreal, QC, Canada (2011).

18) A. D. Franklin, S. O. Koswatta, and W. Haensch, “Suitability of carbon nanotube transistors for low-voltage electronics,” GOMAC Tech, Orlando, FL (2011).

17) S.-J. Han, J. Chang, A. D. Franklin, A. A. Bol, R. Loesing, D. Guo, G. S. Tulevski, W. Haensch, and Z. Chen, “Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates,” IEEE International Electron Device Meeting (IEDM), San Francisco, CA (2010).

16) A. D. Franklin, A. A. Bol, T. O. Graham, and Z. Chen, “Contact geometry effects on graphene transistor performance,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2010).

15) A. D. Franklin, A. A. Bol, and Z. Chen, “Channel and contact length scaling in carbon nanotube transistors” Device Research Conference, Notre Dame, South Bend, IN (2010).   

14) G. Tulevski, A. Afzali, and A. D. Franklin, “Fabrication of sub-micron, multi-channel, single walled carbon nanotube devices,” APS March Meeting, Portland, OR (2010).

13) A. D. Franklin, G. Tulevski, J. B. Hannon, Z. Chen, “Can carbon nanotube transistors be scaled without performance degradation?” IEEE International Electron Device Meeting (IEDM), Baltimore, MD (2009).

12) A. D. Franklin, G. Tulevski, J. Hannon, Z. Chen, “Local bottom gating for high performance carbon nanotube array transistors,” Materials Research Society (MRS) Fall  Meeting, Boston, MA (2009).

11) A. D. Franklin, T. S. Fisher, “Toward manufacturable nanoelectronics using templated vertical carbon nanotubes,” GOMAC Tech, Orlando, FL (2009).

10) A. D. Franklin, J. C. Claussen, R. A. Sayer, T. D. Sands, D. B. Janes, T. S. Fisher, "Vertically aligned arrays of templated single-walled carbon nanotubes for nanoelectronics," Materials Research Society (MRS) Fall Meeting, Boston, MA (2008).

9) A. D. Franklin, J. Zuidema, T. S. Fisher, “Fabrication of porous anodic titania thin films for application in solar cells,” Joint India-US Workshop on Scalable Nanomaterials for Enhanced Energy Transport, Conversion and Efficiency, Bangalore, India (2008).

8) A. D. Franklin, R. A. Sayer, T. D. Sands, D. B. Janes, T. S. Fisher, "Templated vertical carbon nanotube devices with wrap-around gating," International Conference on Nanoscience and Technology (ICN-T), Keystone, CO (2008).

7) R. A. Sayer, S. Kim, A. D. Franklin, C. Lan, R. G. Reifenberger, S. Mohammadi, T. S. Fisher, "Measurement of thermal resistance by shot noise in carbon nanotubes," International Conference on Nanoscience and Technology (ICN-T), Keystone, CO (2008).

6) A. D. Franklin, R. A. Sayer, J. C. Claussen, T. D. Sands, D. B. Janes, T. S. Fisher, "Self-aligned ordered arrays of vertical carbon nanotubes with controllable lengths," Electronic Materials Conference, Santa Barbara, CA (2008).

5) T. L. Westover, A. D. Franklin, R. G. Reifenberger, T. S. Fisher, "Photo-enhanced thermionic emission from potassium-intercalated carbon nanotube arrays," Proc. of 3rd Energy Nanotech. International Conference (ENIC2008), Jacksonville, FL (2008).

4) J. T. Smith, A. D. Franklin, Q. Hang, T. S. Fisher, T. D. Sands, D. B. Janes, “Silicon supported porous anodic alumina templates with long-range order for vertical nanoscale devices,” Electronic Materials Conference, South Bend, IN (2007).

3) A. D. Franklin, J. T. Smith, T. D. Sands, T. S. Fisher, D. B. Janes, “Semi-vertical SWNT FETs: Steps towards verticality and manufacturability,” Nano and Giga Challenges in Electronics and Photonics, Phoenix, AZ (2007).

2) A. D. Franklin, J. T. Smith, M. R. Maschmann, D. B. Janes, T. Sands, T. S. Fisher, “Lithography-free in situ ohmic contacts to single-walled carbon nanotubes,” Materials Research Society (MRS) Fall Meeting, Boston, MA (2006).

1) A. D. Franklin, M. R. Maschmann, M. DaSilva, T. Sands, D. B. Janes, T. S. Fisher, “Contact metallization process for vertical carbon nanotube arrays templated in porous anodic alumina,” Electronic Materials Conference, State College, PA (2006).

 

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